points by westurner 3 years ago

From the abstract; "Pushing the Limits of Machine Design: Automated CPU Design with AI" (2023) https://arxiv.org/abs/2306.12456 :

> [...] This approach generates the circuit logic, which is represented by a graph structure called Binary Speculation Diagram (BSD), of the CPU design from only external input-output observations instead of formal program code. During the generation of BSD, Monte Carlo-based expansion and the distance of Boolean functions are used to guarantee accuracy and efficiency, respectively. By efficiently exploring a search space of unprecedented size 10^{10^{540}}, which is the largest one of all machine-designed objects to our best knowledge, and thus pushing the limits of machine design, our approach generates an industrial-scale RISC-V CPU within only 5 hours. The taped-out CPU successfully runs the Linux operating system and performs comparably against the human-designed Intel 80486SX CPU. In addition to learning the world's first CPU only from input-output observations, which may reform the semiconductor industry by significantly reducing the design cycle, our approach even autonomously discovers human knowledge of the von Neumann architecture.

The von Neumann (and Mark) architectures have an instruction pipeline bottleneck maybe by design for serial debuggability; as compared with IDK in-RAM computing with existing RAM geometries? (See also: "Rowhammer for qubits")

(Edit: High-Bandwidth Memory; hbm2e vs gddr6x (2023) https://en.wikipedia.org/wiki/High_Bandwidth_Memory )

Hopefully part of the fitness function is determined by the presence and severity of hardware side channels and electron tunneling; does it filter out candidate designs with side-channel vulnerabilities (that are presumed undetectable with TLA+)?